1. Field of the Invention
This invention relates in general to a Cache memory system for use in computers and more specifically relates to a metal oxide-semiconductor (MOS) analog multi-bit comparator sense amplifier and MOS analog exclusive-OR (XOR) amplifier for performing the comparison and XOR functions normally performed by digital circuits in computers and to a Cache memory system employing such amplifiers.
2. Description of the Prior Art
In a high speed computer system utilizing high speed central processing unit (CPU), such as the i80386 or i80486 CPU of Intel Corp., the memory data access is a major bottleneck of the throughput of such computer system. To eliminate this bottleneck and increase the throughput, a small and high-speed Cache memory subsystem is added between the CPU and the main memory. The Cache memory increases the effective speed of the main memory by responding quickly with a copy of the most frequently used main memory data. When the CPU tries to read data from the main memory, the high-speed Cache memory will respond first to check if it has a copy of the requested data. Otherwise, a normal main memory cycle will take place. FIG. 1 depicts the Cache memory system arrangement of modern computer system.
A typical Cache memory subsystem consists of Tag Random Access Memory (Tag RAM), Data RAM, both being usually in form of high speed Static RAM (SRAM) and control logic. The Data RAM stores a copy of the most frequently used main memory data. The Tag RAM stores addresses of the most frequently used main memory having a copy in Data RAM. When the CPU sends out the address of main memory it tries to access, the Tag RAM makes a comparison between the external CPU address and the data stored in the Tag RAM to determine it is a HIT or a MISS. If it is a HIT, data is accessed from the Cache Data RAM. Otherwise, the data is accessed from the main memory. The HIT and MISS signals appear at the MATCH outputs of the Cache Tag RAMs in FIG. 1. The Memory Read/Write Control Logic then controls the reading and writing of data from the Cache Data RAM or the main memory in response to the HIT, MISS signals.
The performance of the Cache memory subsystem is largely dependent on how fast the Tag RAM can do the Cache Tag comparison or, in other words, the comparison between the address provided by the CPU on the address lines and the addresses stored in the Cache Tag RAMs. Therefore, improving the Tag comparison speed in the Tag RAM becomes a very important design issue in a Cache memory subsystem.
For detailed treatments on the state of art Cache Tag RAM, please refer to "Cache Tag RAM Chips Simplify Cache Memory Design," by David C. Wyland in the Application Note AN-07 by Integrated Device Technology, Inc. of Santa Clara, Calif.
In order to achieve high performance Tag comparison speed, a very advanced manufacturing technology, such as sub-micron complementary-metal-oxide-semiconductor (CMOS) technology or bipolar technology, is usually required. However, those technologies are very complicated and therefore costly.
FIG. 2 depicts a conventional multi-bit Tag comparison architecture which forms a part of the Cache Tag RAM. Data is first read out from the Tag static RAM (SRAM) as differential signals and appear on the bit lines. Since the differential signals representative of the data are of the order of only several hundred millivolts, they are first amplified and converted into CMOS level signal by the sense amplifier. The CMOS level data output from the sense amplifier then are compared with the CPU address A0, . . . , An-1 by a digital comparator to determine a HIT or MISS condition. The prior art digital comparator (shown within dotted lines in FIG. 2) consists of N XOR and one not-OR (NOR) gate with N inputs for making N bits data comparison, as shown in FIG. 2. Every XOR makes XOR comparison of each bit and the results are combined at the NOR. These gates are switched between the logic level "1" and "0" by turning the MOSFETs in the XOR- and NOR-gates, either N-channel MOS (NMOS) or P-channel MOS (PMOS), on and off.
In the physical chip layout, not shown in this application, the interconnection line between the XORs and the NOR are often very long, thereby causing substantial parasitic line capacitance along the interconnection path. In order to drive substantial capacitance between 0 and 5 volts, the logic gates used need to have more driving capability. This requirement makes the logic gate capacitance large. Due to the large line capacitance and gate capacitance, it is difficult to achieve high speed performance unless an advanced process technology is utilized.
Digital comparators operated by turning the MOS on and off at very high speed generate switching noise, in addition to the power bouncing problem.